1. Field Of The Invention
The present invention relates to an electrically rewritable non-volatile semiconductor memory device, such as a flash EEPROM or the like.
2. Description Of The Prior Art
A memory cell array consisting of a plurality of memory cells is provided in a non-volatile semiconductor memory device, such as a flash Electrically Erasable and Programmable Read Only Memory (EEPROM) which can electrically rewrite data. Each of the memory cells is formed with a MOSFET. In each of the memory cells, a substrate with a source and a drain on the surface, a control gate electrically insulated from the substrate, and a floating gate formed between the substrate and the control gate are provided. It should be noted that the floating gate is electrically insulated from the substrate and the control gate. Furthermore, the drain, the source and the control gate are connected through wiring.
In such a non-volatile semiconductor memory device, data is stored by charging electron in the floating gate. On the other hand, data is erased by discharging electron from the floating gate. When the electron charged in the floating gate is to be discharged, no voltage is applied to the drain of the memory cell, a voltage of 0V is applied to the control gate of the memory cell, and an electron discharging voltage, e.g. 12V is applied to the source of the memory cell. In such condition, potential of the source of the memory cell becomes much higher than potential of the floating gate to flow the Fowler-Nordheim type tunnel current from the source to the floating gate. Since electron flows in the opposite direction to a flow direction of a current, electron is discharged from the floating gate to the source.
In general, the wiring connected to the source is connected to a source voltage control circuit. The voltage for discharging electron is supplied from the source voltage control circuit. FIG. 1 is a circuit diagram of a conventional source voltage control circuit. The conventional source voltage control circuit is formed with one p-channel MOS transistor. Then, a voltage of 0V is applied to the gate thereof, and a voltage of 12V is supplied to the source. On the other hand, the drain of the p-channel MOS transistor is connected to the sources of the memory cells. FIG. 2 is a graph showing a load characteristics of the conventional source voltage control circuit with taking a voltage output to the source's of the memory cells on the horizontal axis and a current output to the sources on the vertical axis. It should be noted that, in FIG. 2, the solid line represents a load characteristics of the source voltage control circuit, and the broken line represents a source current characteristics of the memory cell. The source current characteristics of the memory cell is determined by the number of electron charged in the floating gate and thus is variable depending on an elapsed time during the discharging electron process, as shown in FIG. 2. Then, the current I.sub.s flowing through the source and the voltage V.sub.s applied to the source of the memory cell in the memory cell array is derived from an intersection of a curve representing the load characteristics of the source voltage control circuit and a curve representing the source current characteristics of the memory cell. Namely, during the discharging electron process, as time elapses the source voltage V.sub.s become elevated and the source current Is become lowered.
On the other hand, during the discharge electron process, since electron is discharged from the floating gate, the potential of the floating gate is also elevated. Comparing speed of elevating of the source voltage V.sub.s of the memory cell and speed of elevating of the potential of the floating gate, the later speed is higher. Accordingly, in the initial stage of the discharging electron process, the highest electric field is applied to a tunnel film existing between the source and the floating gate to flow the largest current in the discharging electron process.
Then, by a high electric field applied initially in the discharging electron process, the tunnel film is depleted to cause bad influence on repetition characteristics of rewriting of data and data holding characteristics after rewriting of data.
Therefore, there has been proposed a non-volatile semiconductor memory device prevented from degradation of characteristics of the memory cell (Japanese Unexamined Patent Publication No. Hei 5-182483). FIG. 3 is a circuit diagram showing a source voltage control circuit disclosed in Japanese Unexamined Patent Publication No. Hei 5-182483. In the source voltage control circuit disclosed in the above-identified publication, a p-channel MOS transistor 101, a depression type n-channel MOS transistor 102 and an n-channel MOS transistor 103 are connected in series. Input terminals, to which input signals are input, are connected to a gate of the p-channel MOS transistor 101 and a gate of the n-channel MOS transistor 103. On the other hand, a gate of the n-channel MOS transistor 102 is connected to a junction 104 between the n-channel MOS transistor 102 and the n-channel MOS transistor 103. Furthermore, sources of memory cells in a memory cell array are also connected to the junction 104. On the other hand, a drain saturated current of the n-channel MOS transistor 102 is set: lower than or equal to a predetermined current.
In the conventional source voltage control circuit constructed as set forth above, since the drain saturated current is set to be lower than or equal to the predetermined current, occurrence of a high electric field in the initial state of the discharge electron process can be prevented. However, the foregoing source voltage control circuit includes the depletion type n-channel MOS transistor whose threshold voltage is lower than or equal to 0V. For fabricating the depletion type n-channel MOS transistor, a step of diffusing impurity to a channel region is required. Accordingly, greater number of photoresists become necessary for fabrication of such a depletion type n-channel MOS transistor in comparison with an enhanced type n-channel MOS transistor and a p-channel MOS transistor, and thus greater number of process steps are required.
On the other hand, there has been also proposed a non-volatile semiconductor memory device having a source voltage control circuit which controls rising period of a voltage applied to sources of memory cells (Japanese Unexamined Patent Publication No. Hei 6-37285). FIG. 4 is a circuit diagram showing a source voltage control circuit disclosed in the above-identified Japanese Unexamined Patent Publication No. Hei 6-37285. In the disclosed source voltage control circuit, a boosting circuit 201 converting an erasure signal into a gradually rising voltage and an output circuit 202 outputting a voltage output from the boosting circuit 201 to sources of memory cells in memory cell array are provided. In the boosting circuit 201, a gate of an n-channel MOS transistor 201b and an input terminal of an inverter 201c are connected to an input terminal, to which the erasure signal is input. Ai gate of a n-channel MOS transistor 201e is connected to an output terminal of the inverter 201c. A drain of a p-channel MOS transistor 201a is connected to a drain of the n-channel MOS transistor 201b. Also, respective gates of a p-channel MOS transistor 201d, an n-channel MOS transistor 201h and an n-channel MOS transistor 201q are connected to the drain of the n-channel MOS transistor 201b. A drain of the n-channel MOS transistor 201e is connected to a gate of the p-channel MOS transistor 201a, a gate of an n-channel MOS transistor 201f and a drain of the p-channel MOS transistor 201d. A source of a p-channel MOS transistor 201g and a source of an n-channel MOS transistor 201i are connected to a drain of the n-channel MOS transistor 201f. A drain of the p-channel MOS transistor 201g is connected to a drain of the n-channel MOS transistor 201h. One terminal of a capacitor 201l is connected to the source of the n-channel MOS transistor 201i. An input terminal of an inverter 201k is connected to the other terminal of the capacitor 201l. It should be noted that an oscillation signal OSC is supplied to the inverter 201k. One terminal of a capacitor 201m is connected to an output terminal of the inverter 201k. A drain of the n-channel MOS transistor 201i is connected to the other terminal of the capacitor 201m. Also, a source of an n-channel MOS transistor 201j is connected to the drain of the n-channel MOS transistor 201i. A gate of the n-channel MOS transistor 201i is connected to its own source. A gate of the n-channel MOS transistor 201j is connected to its own source. A p-channel MOS transistor 201p, an n-channel MOS transistor 201o and an n-channel MOS transistor 201n are connected to an n-channel MOS transistor 201q in series in sequential order. It should be noted that a voltage V.sub.pp is supplied to a source of the n-channel MOS transistor 201n. A gate of the n-channel MOS transistor 201n is connected to its own source. Also, a gate of the n-channel MOS transistor 201o is connected to its own source. Similarly, a gate of the p-channel MOS transistor 201p is connected to its own source. On the other hand, a drain of the n-channel MOS transistor 201j and the output circuit 202 are connected to a junction between the source of the n-channel MOS transistor 201o and the p-channel MOS transistor 201p. It should be noted that the voltage V.sub.pp is supplied to the source of the p-channel MOS transistor 201a, the source of the n-channel MOS transistor 201d, the drain of the n-channel MOS transistor 201f and the source of the n-channel MOS transistor 201n. On the other hand, a power source voltage V.sub.cc is supplied to the gate of the p-channel MOS transistor 201g and the gate of the p-channel MOS transistor 201p.
On the other hand, in the output circuit 202, a source of a p-channel MOS transistor 202a and a drain of an n-channel MOS transistor 202c is connected to an input terminal, to which the signal output from the boosting circuit 201 is input. An input terminal of an inverter 202b is connected to a drain of the p-channel MOS transistor 202a. A gate of an n-channel MOS transistor 202d is connected to an output terminal of the inverter 202b. A source of the n-channel MOS transistor 202c and a source of the n-channel MOS transistor 202d are connected to sources of memory cells in a memory cell array. On the other hand, the voltage V.sub.pp is supplied to a drain of the n-channel MOS transistor 202c. Also, the power source voltage V.sub.cc is supplied to a gate of the p-channel MOS transistor 202a.
In the conventional source voltage control circuit constructed as set forth above, when the erasure signal is input the boosting circuit 201, the erasure signal is gradually propagated among the respective transistors and converted into a voltage. Then, the voltage is output to the output circuit 202. In the output circuit 202, the voltage output from the boosting circuit 201 is gradually risen up to the voltage V.sub.pp to be output to the sources in the memory cell array. However, the voltage per se in the initial stage of the discharging electron process is not lowered. Therefore, since a high electric field is applied to a tunnel film to cause fatigue of the tunnel film.
Furthermore, there has been proposed a non-volatile semiconductor memory device having means for transiting a threshold voltage to a targeted value from the value on writing in two stages in order to suppress a large current flowing between a source and a substrate (Japanese Unexamined Patent Publication No. Hei 7-235190). In a non-volatile semiconductor memory device disclosed in the above-identified publication, by applying an even voltage to sources of memory cells in two stages, a threshold value of the memory cells transits in two stages. However, in the initial stage of the discharging electron process, the problem that a high electric field is applied to the tunnel film is held unsolved. Furthermore, as can be appreciated from consideration of the source current characteristics of the memory cell and so forth, it is difficult to apply the even voltage to the source of the memory cell within a certain period. However, nothing has been mentioned about load characteristics of the source voltage control circuit and the source current characteristics of the memory cell. Therefore, implementation of the non-volatile semiconductor memory device is impossible.